The technology of chips continues to change and generally this means a further reduction in size. Each reduction in size presents more problems which must be overcome. In particular for smaller devices one of the main issues which arise is the strength or robustness of the chips. This is the case in all parts of the chip but can be more of an issue in the areas where probing or other types of testing are carried out.
The problems of spreading the forces of testing have been discussed in a number of documents with respect to the domain of micro technology (i.e. size ˜10−6 m). For example U.S. Pat. No. 6,563,226 B2 (Motorola) and U.S. Pat. No. 6,717,270 (Motorola) describe the use of probe-over-passivation (POP); bond-over-passivation (BOP) and bond over activated layer (BOA) processes.
US 200005/0121803 A1 relates to an internally reinforced bond pad. The reinforced bond pad has a non planar dielectric structure and a metallic bond layer which conforms with this non-planar dielectric structure. This invention requires a dual inlaid bonding surface (which needs a very complex process with many steps). U.S. Pat. No. 6,531,384 B1 discloses a so called “armoured” bond pad. This patent teaches a structure having a number of islands of copper metal 18 extending above the insulation 14. In addition this patent deals with bonding and probing in the same area. The metal dielectric pattern is an uppermost metal e.g. aluminium and would not be compatible with fine-pitch bond pads. This also limits bond over activation (BOA) compatibility because the bonding surface must be electrically connected by underlying metal layers. The alternation of copper islands and passivation provides vertical connectivity. To make this alternation of copper islands and passivation layer requires a number of additional steps of processing which add to the cost and time for making the device.